PCLK_FORCE=Val_0x0, IPCLK_FORCE=Val_0x0, PDM_SEL=Val_0x0, PDM_CKEN=Val_0x0, BKRAM_CKEN=Val_0x0
Clock Control Register
| BKRAM_CKEN | Clock enable for Backup SRAM 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| PDM_CKEN | Clocks enable for PDM 0 (Val_0x0): Disable clocks 1 (Val_0x1): Enable clocks |
| PDM_SEL | PDM functional clock source select 0 (Val_0x0): Select 76.8 MHz crystal-oscillator clock (76M8_CLK) 1 (Val_0x1): Select external audio clock input (AUDIO_CLK) |
| PCLK_FORCE | 0 (Val_0x0): Clock force disabled 1 (Val_0x1): Force APB interface clocks (PCLKs) on, bypass clock gating |
| IPCLK_FORCE | 0 (Val_0x0): Clock force disabled 1 (Val_0x1): Force peripherals functional clocks on, bypass clock gating |